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PRELIMINARY
www.dalsemi.com
DS80C390 Dual CAN High-Speed Microprocessor
PIN ASSIGNMENT
48 33
FEATURES
80C52 compatible - 8051 instruction-set compatible - Four 8-bit I/O ports - Three 16-bit timer/counters - 256 bytes scratchpad RAM High-Speed Architecture - 4 clocks/machine cycle (8051=12) - Runs DC to 40 MHz clock rates - Frequency multiplier reduces EMI - Single-cycle instruction in 100 ns - 16/32-bit math coprocessor 4 kB internal SRAM usable as program/data/stack memory Enhanced memory architecture - Addresses up to 4 MB external - Defaults to true 8051 memory compatibility - User-enabled 22-bit program/data counter - 16-Bit/22-bit paged/22-bit contiguous modes - User-selectable multiplexed / nonmultiplexed memory interface - Optional 10 bit stack pointer Two full-function CAN 2.0B controllers - 15 message centers per controller - Standard 11-bit or extended 29-bit identification modes - Supports DeviceNet, SDS, and higher layer CAN protocols - Disables transmitter during autobaud - SIESTA low power mode Two full-duplex hardware serial ports Programmable IrDA clock High integration controller includes - Power-fail reset - Early-warning power-fail interrupt - Programmable watchdog timer - Oscillator-fail detection 16 total interrupt sources with 6 external Available in 64-pin QFP, 68-pin PLCC 1 of 58
49
32
DS80C390
64
17

1
16
64-PIN QFP
9 1 61
10
60
DS80C390
26
44
27
43
68-PIN PLCC

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DS80C390
DESCRIPTION
The DS80C390 is a fast 8051-compatible microprocessor. The redesigned processor core executes 8051 instructions up to 3 times faster than the original for the same crystal speed. The DS80C390 supports a maximum crystal speed of 40 MHz, resulting in apparent execution speeds of 100 MHz (approximately 2.5X). An optional internal frequency multiplier allows the microprocessor to operate at full speed with a reduced crystal frequency, reducing EMI. A hardware math accelerator further increases the speed of 32 and 16 bit multiply and divide operations, as well as high-speed shift, normalization and accumulate functions. The DS80C390 features two full-function Controller Area Network (CAN) 2.0B controllers. Status and control registers are distributed between SFRs and 512 bytes of internal MOVX memory for maximum flexibility. In addition to standard 11-bit or 29-extended message identifiers, the device supports two separate 8-bit media masks and media arbitration fields to support the use of higher-level CAN protocols such as DeviceNet and SDS. All of the standard 8051 resources such as three timer/counters, serial port, and four 8-bit I/O ports (plus two 8-bit ports dedicated to memory interfacing) are included in the DS80C390. In addition it includes a second hardware serial port, seven additional interrupts, programmable watchdog timer, brown-out monitor, power-fail reset, and a programmable output clock that supports an IRDA interface. The device provides dual data pointers with increment/decrement features to speed block data memory moves. It also can adjust the speed of MOVX data memory access from two to twelve machine cycles for flexibility in addressing external memory and peripherals. The device incorporates a 4kB SRAM, which can be configured as various combinations of MOVX memory, program memory, and optional stack memory. A 22-bit program counter supports access to a maximum of 4 MB of external program memory and 4 MB of external data memory. A 10-bit stack pointer addresses up to 1kB of MOVX memory for increased code efficiency. A new Power Management Mode (PMM) is useful for portable or power-conscious applications. This feature allows software to switch from the standard machine cycle rate of 4 clocks per cycle to 1024 clocks per cycle. For example, at 12 MHz standard operation has a machine cycle rate of 3 MHz. In Power Management Mode at the same external clock speed, software can select 11.7 kHz machine cycle rate. There is a corresponding reduction in power consumption when the processor runs slower. The EMI reduction feature allows software to select a reduced electromagnetic interference (EMI) mode by disabling the ALE signal when it is unneeded. The device also incorporates active current control on the address and data buses, reducing EMI by minimizing transients when interfacing to external circuitry.
ORDERING INFORMATION
Part Number DS80C390-QCR DS80C390-FCR DS80C390-QNR DS80C390-FNR Package 68-pin PLCC 64-pin LQFP 68-pin PLCC 64-pin LQFP Max. Clock Speed 40 MHz 40 MHz 40 MHz 40 MHz Temperature Range 0C to +70C 0C to +70C -40C to +85C -40C to +85C
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DS80C390 BLOCK DIAGRAM Figure 1
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PIN DESCRIPTION Table 1
LQFP 8, 22, 40, 56 9, 25, 41, 57 46 PLCC 17, 32, 51, 68 1, 18, 35, 52 57 SIGNAL NAME VCC GND ALE DESCRIPTION +5V Digital Circuit Ground Address Latch Enable - Output. When the MUX pin is low, this pin outputs a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. When the MUX pin is high, the pin will toggle continuously if the ALEOFF bit is cleared. ALE is forced high when the device is in a Reset condition or if the ALEOFF bit is set while the MUX pin is high. Program Store Enable - Output. This signal is the chip enable for external ROM memory. PSEN provides an active low pulse and is driven high when external ROM is not being accessed. External Access Enable - Input. This pin must be tied to GND for proper operation. Multiplex/Demultiplex Select - Input. This pin selects if the address/data bus operates in multiplexed ( MUX =0) or demultiplexed ( MUX =1) mode. Reset - Input. The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wired OR external Reset sources. An RC circuit is not required for power-up, as the device provides this function internally. Reset Output Low - Output. This active low signal will be asserted: When the processor has entered reset via the RST pin, During crystal warm-up period following power-on or Stop mode, During a watchdog timer reset (2 cycles duration), During an oscillator failure (if OFDE=1), Whenever VCC VRST XTAL1, XTAL2 - Crystal oscillator pins support fundamental mode, parallel resonant, AT cut crystals. XTAL1 is the input if an external clock source is used in place of a crystal. XTAL2 is the output of the crystal amplifier. AD0-7 (Port 0) - I/O. When the MUX pin is tied low, Port 0 is the multiplexed address/data bus. While ALE is high, the LSB of a memory address is presented. While ALE falls, the port transitions to a bi-directional data bus. When the MUX pin is tied high, Port 0 functions as the bi-directional data bus. Port 0 cannot be modified by software. The reset condition of Port 0 pins is high. No pullup resistors are needed. 4 of 58 110199
45
56
PSEN
47 26
58 36
EA
MUX
2
11
RST
3
12
RSTOL
23, 24
33, 34
XTAL2, XTAL1
55 54 53 52 51 50 49 48
67 66 65 64 63 62 61 59
AD0 / D0 AD1 / D1 AD2 / D2 AD3 / D3 AD4 / D4 AD5 / D5 AD6 / D6 AD7 / D7
DS80C390
58-64, 1
2-8, 10
P1.0-P1.7
58 59 60 61 62 63 64 1 35 36 37 38 39 42 43 44 4-7, 10-13
2 3 4 5 6 7 8 10 46 47 48 49 50 53 54 55 13-16, 19-22
A0 A1 A2 A3 A4 A5 A6 A7 A8 (P2.0) A9 (P2.1) A10 (P2.2) A11 (P2.3) A12 (P2.4) A13 (P2.5) A14 (P2.6) A15 (P2.7) P3.0-P3.7
Port 1 - I/O. Port 1 can function as an 8-bit bi-directional I/O port, the non-multiplexed A0 - A7 signals (when the MUX pin =1), and as an alternate interface for internal resources. Setting the SP1EC bit relocates RXD1 and TXD1 to Port 5. The reset condition of Port 1 is all bits at logic 1 via a weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. When software clears any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 will activate a strong transition driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again becomes the output (and input) high state. Port Alternate Function P1.0 T2 External I/O for Timer/Counter 2 P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger P1.2 RXD1 Serial Port 1 Input P1.3 TXD1 Serial Port 1 Output P1.4 INT2 External Interrupt 2 (Pos. Edge Detect) P1.5 INT3 External Interrupt 3 (Neg. Edge Detect) P1.6 INT4 External Interrupt 4 (Pos. Edge Detect) P1.7 INT5 External Interrupt 5 (Neg. Edge Detect) A15-A8 (Port 2) - Output. Port 2 serves as the MSB for external addressing. The port automatically asserts the address MSB during external ROM and RAM access. Although the Port 2 SFR exists, the SFR value will never appear on the pins (due to memory access). Therefore accessing the Port 2 SFR is only useful for MOVX A, @Ri or MOVX @Ri, A instructions, which use the Port 2 SFR as the external address MSB. Port 3 - I/O. Port 3 functions as an 8-bit bi-directional I/O port, and as an alternate interface for several resources found on the traditional 8051. The reset condition of Port 1 is all bits at logic 1 via a weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 will activate a strong transition driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again becomes the output (and input) high state. Port Alternate Function P3.0 RXD0 Serial Port 0 Input P3.1 TXD0 Serial Port 0 Output P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 External Input P3.5 T1/XCLK Timer 1 External Input/External Clock Output P3.6 WR External Data Memory Write Strobe 5 of 58 110199
4 5 6 7 10 11 12
13 14 15 16 19 20 21
DS80C390
13 34-27
22 45, 44, 42-37
P4.0-P4.7
34 33 32 31 30 29 28 27 21-14
45 44 42 41 40 39 38 37 31-27, 25-23
P5.0-P5.7
21 20 19 18 17 16 15 14
31 30 29 28 27 25 24 23 9, 26, 43, 60
P3.7 RD External Data Memory Read Strobe Port 4 - I/O. Port 4 can function as an 8-bit bi-directional I/O port, and as the source for external address and chip enable signals for program and data memory. Port pins are configured as I/O or memory signals via the P4CNT register. The reset condition of Port 1 is all bits at logic 1 via a weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 will activate a strong transition driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again becomes the output (and input) high state. Port Alternate Function P4.0 CE0 Program Memory Chip Enable 0 P4.1 CE1 Program Memory Chip Enable 1 P4.2 CE2 Program Memory Chip Enable 2 P4.3 CE3 Program Memory Chip Enable 3 P4.4 A16 Program/Data Memory Address 16 P4.5 A17 Program/Data Memory Address 17 P4.6 A18 Program/Data Memory Address 18 P4.7 A19 Program/Data Memory Address 19 Port 5 - I/O. Port 5 can function as an 8-bit bi-directional I/O port, the CAN interface, or as peripheral enable signals. Setting the SP1EC bit will relocate the RXD1 and TXD1 functions to P5.3P5.2 as described in the User's Guide. The reset condition of Port 1 is all bits at logic 1 via a weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 will activate a strong transition driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again becomes the output (and input) high state. Port Alternate Function P5.0 C0TX CAN0 Transmit Output P5.1 C0RX CAN0 Receive Input P5.2 C1RX CAN1 Receive Input (optional RXD1) P5.3 C1TX CAN1 Transmit Output (optional TXD1) P5.4 PCE0 Peripheral Chip Enable 0 P5.5 PCE1 Peripheral Chip Enable 1 P5.6 PCE2 Peripheral Chip Enable 2 P5.7 PCE3 Peripheral Chip Enable 3 NC - Reserved. These pins are reserved for use with future devices in this family and should not be connected. 6 of 58 110199
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80C32 COMPATIBILITY
The DS80C390 is a CMOS 80C32-compatible microcontroller designed for high performance. Every effort has been made to keep the core device familiar to 80C32 users while adding many new features. Because the device runs the standard 8051 instruction set, in general software written for existing 80C32based systems will work on the DS80C390. The primary exceptions are related to timing-critical issues, since the high-performance core of the microcontroller executes instructions much faster than the original. Memory interfacing is performed identically to the standard 80C32. The high-speed nature of the DS80C390 core will slightly change the interface timing, and designers are advised to consult the timing diagrams in this data sheet for more information. The DS80C390 provides the same timer/counter resources, full duplex serial port, 256 bytes of scratchpad RAM and I/O ports as the standard 80C32. Timers will default to a 12 clocks per machine cycle operation to keep timing compatible with original 8051 systems, but can be programmed to run at the faster 4 clocks per machine cycle if desired. New hardware functions are accessed using Special Function Registers that do not overlap with standard 80C32 locations. This data sheet provides only a summary and overview of the DS80C390. Detailed descriptions are available in the corresponding user's guide. This data sheet assumes a familiarity with the architecture of the standard 80C32. In addition to the basic features of that device, the DS80C390 incorporates many new features.
PERFORMANCE OVERVIEW
The DS80C390's higher performance comes not just from increasing the clock frequency, but from a more efficient design. This updated core removes the dummy memory cycles that are present in a standard, 12 clocks per machine cycle 8051. In the DS80C390, the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine cycle, executes 3 times faster for the same crystal frequency. The majority of instructions on the DS80C390 will see the full 3 to 1 speed improvement, while a few will execute between 1.5 and 2.4 times faster. Regardless of specific performance improvements, all instructions are faster than the original 8051. Improvement of individual programs will depend on the actual mix of instructions used. Speed sensitive applications should make the most use of instructions that are 3 times faster. However, the large number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any arbitrary combination of instructions. These architecture improvements and the sub-micron CMOS design produce a peak instruction cycle in 100 ns (10 MIPs). The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions perform exactly the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is identical. However, the timing of instructions is different, both in absolute and relative number of clocks. The absolute timing of software loops can be calculated using a table in the user's guide. However, counter/timers default to run at the traditional 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at the faster 4 clocks per increment to take advantage of faster processor operation. The relative time of two DS80C390 instructions might differ from the traditional 8051. For example, in the original architecture the "MOVX A, @DPTR" instruction and the "MOV direct, direct" instruction 7 of 58 110199
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required the same amount of time: two machine cycles or 24 oscillator cycles. In the DS80C390, the MOVX instruction takes as little as two machine cycles or 8 oscillator cycles but the "MOV direct, direct" uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the device usually uses one instruction cycle for each instruction byte. Examine the timing of each instruction for familiarity with the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. Refer to the user's guide for details and individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the microcontroller. This allows the device to have many new features but use the same instruction set as the 8051. When writing software to use a new feature, an equate statement defines the SFR to an assembler or compiler. This is the only change needed to access the new function. The DS80C390 duplicates the SFRs contained in the standard 80C52. Table 2 shows the register addresses and bit locations. Many are standard 80C52 registers. The user's guide contains a full description of all SFRs.
SPECIAL FUNCTION REGISTER LOCATION Table 2
Register
P4 SP DPL DPH DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 EXIF P4CNT DPX DPX1 C0RMS0 C0RMS1 SCON0 SBUF0 ESP AP ACON C0TMA0 C0TMA1 P2 P5 P5CNT C0C C0S
Bit7
P4.7
Bit6
P4.6
Bit5
P4.5
Bit4
P4.4
Bit3
P4.3
Bit2
P4.2
Bit1
P4.1
Bit0
P4.0
ADDRESS
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 90h 91h 92h 93h 95h 96h 97h 98h 99h 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h
ID1 SMOD_0 TF1 GATE
ID0 SMOD0 TR1 C/ T
TSL OFDF TF0 M1
OFDE TR0 M0
GF1 IE1 GATE
GF0 IT1 C/ T
STOP IE0 M1
SEL IDLE IT0 M0
WD1 WD0 T2M T1M T0M MD2 MD1 INT5/P1.7 INT4/P1.6 INT3/P1.5 INT2/P1.4 TXD1/P1.3 RXD1/P1.2 T2EX/P1.1 IE5 IE4 IE3 IE2 CKRY RGMD RGSL SBCAN P4CNT.5 P4CNT.4 P4CNT.3 P4CNT.2 P4CNT.1
MD0 T2/P1.0 BGS P4CNT.0
SM0/FE_0 -
SM1_0 -
SM2_0 -
REN_0 -
TB8_0 -
RB8_0 SA
TI_0 ESP.1 AM1
RI_0 ESP.0 AM0
P2.7 P5.7 CAN1BA ERIE BSS
P2.6 P5.6 CAN0BA STIE EC96/128
P2.5 P5.5 SP1EC PDE WKS
P2.4 P5.4 C1_I/O SIESTA RXS
P2.3 P5.3 C0_I/O CRST TXS
P2.2 P5.2 P5CNT.2 AUTOB ER2
P2.1 P5.1 P5CNT.1 ERCS ER1
P2.0 P5.0 P5CNT.0 SWINT ER0
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C0IR C0TE C0RE IE SADDR0 SADDR1 C0M1C C0M2C C0M3C C0M4C C0M5C P3 C0M6C C0M7C C0M8C C0M9C C0M10C IP SADEN0 SADEN1 C0M11C C0M12C C0M13C C0M14C C0M15C SCON1 SBUF1 PMR STATUS MCON TA T2CON T2MOD RCAP2L RCAP2H TL2 TH2 COR PSW MCNT0 MCNT1 MA MB MC C1RMS0 C1RMS1 WDCON C1TMA0 C1TMA1 ACC C1C C1S C1IR C1TE C1RE
INTIN7
INTIN6
INTIN5
INTIN4
INTIN3
INTIN2
INTIN1
INTIN0
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
MSRDY MSRDY MSRDY MSRDY MSRDY P3.7 MSRDY MSRDY MSRDY MSRDY MSRDY -
ETI ETI ETI ETI ETI P3.6 ETI ETI ETI ETI ETI PS1
ERI ERI ERI ERI ERI T1 ERI ERI ERI ERI ERI PT2
INTRQ INTRQ INTRQ INTRQ INTRQ T0 INTRQ INTRQ INTRQ INTRQ INTRQ PS0
EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ INT1 EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ PT1
MTRQ MTRQ MTRQ MTRQ MTRQ INT0 MTRQ MTRQ MTRQ MTRQ MTRQ PX1
ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH TXD0 ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH PT0
DTUP DTUP DTUP DTUP DTUP RXD0 DTUP DTUP DTUP DTUP DTUP PX0
MSRDY MSRDY MSRDY MSRDY MSRDY SM0/FE_1 CD1 PIP IDM1 TF2 -
ETI ETI ETI ETI ETI SM1_1 CD0 HIP IDM0 EXF2 -
ERI ERI ERI ERI ERI SM2_1 SWB LIP CMA RCLK -
INTRQ INTRQ INTRQ INTRQ INTRQ REN_1 CTM TCLK D13T1
EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ TB8_1 4X/ 2X SPTA1 PDCE3 EXEN2 D13T2
MTRQ MTRQ MTRQ MTRQ MTRQ RB8_1 ALEOFF SPRA1 PDCE2 TR2 -
ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH TI_1 SPTA0 PDCE1 C/ T2 T2OE
DTUP DTUP DTUP DTUP DTUP RI_1 SPRA0 PDCE0 CP/ RL2 DCEN
DS80C390 A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh D0h D1h D2h D3h D4h D5h D6h D7h D8h DEh DFh E0h E3h E4h E5h E6h E7h
IRDACK CY
LSHIFT
C1BPR7 AC CSE MOF
C1BPR6 F0 SCB -
C0BPR7 RS1 MAS4 CLM
C0BPR6 RS0 MAS3 -
COD1 OV MAS2 -
COD0 F1 MAS1 -
CLKOE P MAS0 -
MST
SMOD_1
POR
EPFI
PFI
WDIF
WTRF
EWT
RWT
ERIE BSS INTIN7
STIE CECE INTIN6
PDE WKS INTIN5
SIESTA RXS INTIN4
CRST TXS INTIN3
AUTOB ER2 INTIN2
ERCS ER1 INTIN1
SWINT ER0 INTIN0
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EIE MXAX C1M1C C1M2C C1M3C C1M4C C1M5C B C1M6C C1M7C C1M8C C1M9C C1M10C EIP C1M11C C1M12C C1M13C C1M14C C1M15C
CANBIE MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY CANBIP MSRDY MSRDY MSRDY MSRDY MSRDY
C0IE ETI ETI ETI ETI ETI ETI ETI ETI ETI ETI C0IP ETI ETI ETI ETI ETI
C1IE ERI ERI ERI ERI ERI ERI ERI ERI ERI ERI C1IP ERI ERI ERI ERI ERI
EWDI INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ PWDI INTRQ INTRQ INTRQ INTRQ INTRQ
EX5 EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ PX5 EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ
EX4 MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ PX4 MTRQ MTRQ MTRQ MTRQ MTRQ
EX3 ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH PX3 ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH
EX2 DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP PX2 DTUP DTUP DTUP DTUP DTUP
DS80C390 E8h EAh EBh ECh EDh EEh EFh F0h F3h F4h F5h F6h F7h F8h FBh FCh FDh FEh FFh
*Shaded bits are Timed Access protected.
ON-CHIP ARITHMETIC ACCELERATOR
An on-chip math accelerator allows the microcontroller to perform 32- and 16-bit multiplication, division, shifting, and normalization using dedicated hardware. Math operations are performed by sequentially loading three special registers. The mathematical operation is determined by the sequence in which three dedicated SFRs (MA, MB and MC) are accessed, eliminating the need for a special step to choose the operation. The normalize function facilitates the conversion of 4-byte unsigned binary integers into floating point format. The following table shows the operations supported by the math accelerator and their time of execution.
ARITHMETIC ACCELERATOR EXECUTION TIMES Table 3
Operation 32-bit/16-bit divide 16-bit/16-bit divide 16-bit/16-bit multiply 32-bit shift left/right 32-bit normalize Result 32-bit quotient, 16-bit remainder 16-bit quotient, 16-bit remainder 32-bit product 32-bit result 32-bit mantissa, 5 bit exponent Execution Time 36 tCLCL 24 tCLCL 24 tCLCL 36 tCLCL 36 tCLCL
The following table demonstrates the procedure to perform mathematical operations using the hardware math accelerator. The MA and MB registers must be loaded and read in the order shown for proper operation, although accesses to any other registers can be performed between access to the MA or MB registers. An access to the MA, MB, or MC registers out of sequence will corrupt the operation, requiring the software to clear the MST bit to restart the math accelerator state machine. Consult the description of the MCNT0 SFR for details of how the shift and normalize functions operate.
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ARITHMETIC ACCELERATOR SEQUENCING
Divide (32/16 or 16/16) Load MA with dividend LSB. Load MA with dividendLSB+1* Load MA with dividend LSB+2* Load MA with dividend MSB. Load MB with divisor LSB. Load MB with divisor MSB. Poll the MST bit until cleared (9 machine cycles). Read MA to retrieve the quotient MSB. Read MA to retrieve the quotient LSB+2. Read MA to retrieve the quotient LSB+1. Read MA to retrieve the quotient LSB. Read MB to retrieve the remainder MSB. Read MB to retrieve the remainder LSB. *Not performed for 16 bit numerator. Shift Right/Left Load MA with data LSB. Load MA with data LSB+1. Load MA with data LSB+2. Load MA with data MSB. Configure MCNT0 register as required Poll the MST bit until cleared. (9 machine cycles) Read MA for result MSB. Read MA for result LSB+2. Read MA for result LSB+1. Read MA for result LSB. Multiply (16x16) Load MB with multiplier LSB. Load MB with multiplier MSB. Load MA with multiplicand LSB. Load MA with multiplicand MSB. Poll the MST bit until cleared (6 machine cycles). Read MA for product MSB. Read MA for product LSB+2. Read MA for product LSB+1. Read MA for product LSB.
Normalize Load MA with data LSB. Load MA with data LSB+1. Load MA with data LSB+2. Load MA with data MSB. Configure MCNT0 register as required. Poll the MST bit until cleared (9 machine cycles). Read MA for mantissa MSB. Read MA for mantissa LSB+2. Read MA for mantissa LSB+1. Read MA for mantissa LSB. Read MCNT0.4-MCNT0.0 for exponent.
40-BIT ACCUMULATOR
The accelerator also incorporates an automatic accumulator function, permitting the implementation of multiply-and-accumulate and divide-and-accumulate functions without any additional delay. Each time the accelerator is used for a multiply or divide operation, the result is transparently added to a 40-bit accumulator. This can greatly increase speed of DSP and other high-level math operations. The accumulator can be accessed any time the Multiply/Accumulate Status Flag (MCNT1 ;D2h) is cleared. The accumulator is initialized by performing five writes to the Multiplier C Register (MC ;D5h), LSB first. The 40-bit accumulator can be read by performing five reads of the Multiplier C Register, MSB first.
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MEMORY ADDRESSING
The DS80C390 incorporates three internal memory areas: 256 bytes of scratchpad (or direct) RAM 4 KB of SRAM configurable as various combinations of MOVX data memory, stack memory, and MOVC program memory 512 bytes of RAM reserved for the CAN message centers. Up to 4 MB of external memory is addressed via a multiplexed or demultiplexed 20-bit address bus/8-bit data bus and four chip enable (active during program memory access) or four peripheral enable (active during data memory access) signals. Three different addressing modes are supported, as selected by the AM1, AM0 bits in the ACON SFR. 16-bit address mode 16-bit address mode accesses memory similarly to the traditional 8051. It is opcode compatible with the 8051 microprocessor and identical to the byte and cycle count of the Dallas Semiconductor High-Speed Microcontroller family. A device operating in this mode can access up to 64 KB of program and data memory. The device defaults to this mode following any reset. 22-bit paged address mode The 22-bit paged address mode retains binary code compatibility with the 8051 instruction set, but adds one machine cycle to the ACALL, LCALL, RET and RETI instructions with respect to the Dallas Semiconductor High-Speed Microcontroller family timing. This is transparent to standard 8051 compilers. Interrupt latency is also increased by one machine cycle. In this mode, interrupt vectors are fetched from 0000xxh. 22-bit contiguous address mode The 22-bit contiguous addressing mode uses a full 22-bit program counter, and all modified branching instructions automatically save and restore the entire program counter. The 22-bit branching instructions such as ACALL, AJMP, LCALL, LJMP, MOV DPTR, RET and RETI instructions require an assembler, compiler and linker that specifically supports these features. The INC DPTR is lengthened by one cycle but remains byte count compatible with the standard 8051 instruction set. Internally, the device uses a 22-bit program counter. The lowest order 22 bits are used for memory addressing, with a special 23rd bit used to map the 4KB SRAM above the 4 MB memory space in bootstrap loader applications. Address bits 16-23 for the 22-bit addressing modes are generated via additional SFRs dependent on the type of instruction as shown below.
EXTENDED ADDRESS GENERATION: Table 2
MOVX instructions using DPTR MOVX instructions using DPTR1 MOVX instructions using @Ri Addressing program memory in 22-bit paged mode 10-bit stack pointer mode Address bits 23-16 DPX;93h DPX1;95h MXAX;EAh AP;9Ch -Address bits 15-8 DPH;83h DPH1;85h P2;A0h -ESP;9Bh Address bits 7-0 DPL;82h DPL1;84h Ri -SP;81h
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INTERNAL MOVX SRAM
The DS80C390 contains 4kB of SRAM that can be configured as user accessible MOVX memory, program memory, or optional stack memory. The specific configuration and locations are governed by the Internal Data Memory Configuration bits (IDM1, IDM0) in the Memory Control Register (MCON;C6h). Note that when the SA bit (ACON.2) is set, the first 1kB of the MOVX data memory is reserved for use by the 10-bit expanded stack. Internal memory accesses will not generate WR , RD , or PSEN strobes. The DS80C390 can configure its 4kB of internal SRAM as combined program and data memory. This allows the application software to execute self-modifiable code. The technique loads the 4kB SRAM with bootstrap loader software, and then modifies the IDM1 and IDM0 bits to map the 4kB starting at memory location 40000h. This allows the system to run the bootstrap loader without disturbing the 4 MB external memory bus, making the device in-system reprogrammable for Flash or NV RAM.
INTERNAL MOVX SRAM CONFIGURATION Table 4
CAN Message Memory 0 0 0 00F000h-00FFFFh 00EE00h-00EFFFh 0 0 1 00F000h-00FFFFh 401000h-4011FFh 0 1 0 000000h-000FFFh 00EE00h-00EFFFh 0 1 1 000000h-000FFFh 401000h-4011FFh 1 0 0 400000h-400FFFh 00EE00h-00EFFFh 1 0 1 400000h-400FFFh 401000h-4011FFh 1 1 0 -00EE00h-00EFFFh 1 1 1 -401000h-4011FFh *10-bit expanded stack not available in Shared Program /Data Memory mode. IDM1 IDM0 CMA MOVX Data Memory Shared Program /Data Memory ------400000h-400FFFh* 400000h-400FFFh*
EXTERNAL MEMORY ADDRESSING
The enabling and mapping of the chip enable signals is done via the Port 4 Control Register (P4CNT;92h) and Memory Control Register (MCON; 96h); The Extended Address and Chip Enable Generation Table shows which chip enable and address line signals are active on Port 4. Following reset, the device will be configured with P4.7-P4.4 as address lines and P4.3-P4.0 configured as CE3 - 0 , with the first program fetch being performed from 00000h with CE0 active. The following tables illustrate which memory ranges are controlled by each chip enable as a function of which address lines are enabled.
EXTERNAL MEMORY ADDRESSING PIN ASSIGNMENTS Table 5
Address/Data Bus Multiplexed Demultiplexed
CE3 - CE0 PCE3 - PCE0
P4.3-P4.0 P4.3-P4.0
P5.7-P5.4 P5.7-P5.4
Addr 19-16 Addr 15-8 P4.7-P4.4 P2 P4.7-P4.4 P2
Addr 7-0 P0 P1
Data Bus P0 P0
EXTENDED ADDRESS AND CHIP ENABLE GENERATION Table 6
Port 4 Pin Function P4CNT.5-3 P4.7 P4.6 P4.5 P4.4 000 I/O I/O I/O I/O 100 I/O I/O I/O A16 101 I/O I/O A17 A16 110 I/O A18 A17 A16 111(default) A19 A18 A17 A16 P4CNT.2-0 000 100 101 110 111(default) 13 of 58 Port 4 Pin Function P4.3 P4.2 P4.1 P4.0 I/O I/O I/O I/O I/O I/O I/O CE0 I/O I/O CE1 CE0 I/O CE2 CE1 CE0
CE3 CE2 CE1 CE0
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PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table 7
P4CNT.5-3 000 100 101 110 111(default)
CE0
CE1
CE2
CE3
0h-7FFFh 0h-1FFFFh 0h-3FFFFh 0h-7FFFFh 0-FFFFFh
8000h-FFFFh 20000h-3FFFFh 40000h-7FFFFh 80000h-FFFFFh 100000h-1FFFFFh
10000h-17FFFh 18000h-1FFFFh 40000h-5FFFFh 60000h-7FFFFh 80000h-BFFFFh C0000h-FFFFFh 100000h-17FFFFh 180000h-1FFFFFh 200000h-2FFFFFh 300000h-3FFFFFh
The DS80C390 incorporates a feature allowing PCE and CE signals to be combined. This is useful when incorporating modifiable code memory as part of a bootstrap loader or for in-system reprogrammability. Setting the PDCE3 - 0 (MCON.3-0) bits causes the corresponding chip enable signal to function for both MOVC and MOVX operations. Write access to combined program and data memory blocks is controlled by the WR signal, and read access is controlled by the PSEN signal. This feature is especially useful if the design achieves in-system reprogrammability via external Flash memory, in which a single device is accessed via both MOVC instructions (program fetch) and MOVX Write operations (updates to code memory). In this case, the internal SRAM is placed in the program/data configuration and loaded with a small bootstrap loader program stored in the external Flash memory. The device then executes the internal bootstrap loader routine to modify/update the program memory located in the external Flash memory.
STRETCH MEMORY CYCLES
The DS80C390 allows user application software to select the number of machine cycles it takes to execute a MOVX instruction, allowing access to both fast and slow off-chip data memory and/or peripherals without glue logic. High-speed systems often include memory-mapped peripherals such as LCDs or UARTs with slow access times, so it may not be necessary or desirable to access external devices at full speed. The microprocessor can perform a MOVX instruction in as little as two machine cycles or as many as twelve machine cycles. Accesses to internal MOVX SRAM always use two cycles. Note that stretch cycle settings affect external MOVX memory operations only and that there is no way to slow the accesses to program memory other than to use a slower crystal (or external clock). External MOVX timing is governed by the selection of 0 to 7 Stretch cycles, controlled by the MD2-MD0 SFR bits in the Clock Control Register (CKCON.2-0). A Stretch of zero will result in a two-machine cycle MOVX instruction. A Stretch of seven will result in a MOVX of twelve machine cycles. Software can dynamically change the Stretch value depending on the particular memory or peripheral being accessed. The default of one Stretch cycle allows the use of commonly available SRAMs without dramatically lengthening the memory access times. Stretch cycle settings affect external MOVX timing in three gradations. Changing the Stretch value from 0 to 1 adds an additional clock cycle each to the data setup and hold times. When a Stretch value of 4 or above is selected, the interface timing changes dramatically to allow for very slow peripherals. First, the ALE signal is lengthened by 1 machine cycle. This increases the address setup time into the peripheral by this amount. Next, the address is held on the bus for one additional machine cycle increasing the address hold time by this amount. The WR and RD signals are then lengthened by a machine cycle. Finally, during a MOVX write the data is held on the bus for one additional machine cycle, thereby increasing the data hold time by this amount. For every Stretch value greater than 4, the setup and hold times remain constant, and only the width of the read or write signal is increased. These three gradations are reflected in the AC Electrical characteristics, where the eight MOVX timing specifications are represented by only three timing diagrams. 14 of 58 110199
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The reset default of one Stretch cycle results in a three cycle MOVX for any external access. Therefore, the default off-chip RAM access is not at full speed. This is a convenience to existing designs that utilize slower RAM. When maximum speed is desired, software should select a Stretch value of zero. When using very slow RAM or peripherals, the application software can select a larger Stretch value. The specific timing of MOVX instructions as a function of Stretch settings is provided in the Electrical Specifications section of this data sheet. As an example, Table 8 shows the read and write strobe widths corresponding to each Stretch value.
DATA MEMORY CYCLE STRETCH VALUES Table 8
MD2 MD1 MD0 tMCS tMCS tMCS (4X/ 2X = 1 (4X/ 2X = 0 (4X/ 2X = X CD1:0 = 00) CD1:0 = 00) CD1:0 = 10) 0 0 0 0* 2 0.5 tCLCL 1 tCLCL 2 tCLCL 0 0 1 1** 3 tCLCL 2 tCLCL 4 tCLCL 0 1 0 2 4 2 tCLCL 4 tCLCL 8 tCLCL 0 1 1 3 5 3 tCLCL 6 tCLCL 12 tCLCL 1 0 0 4 9 4 tCLCL 8 tCLCL 16 tCLCL 1 0 1 5 10 5 tCLCL 10 tCLCL 20 tCLCL 1 1 0 6 11 6 tCLCL 12 tCLCL 24 tCLCL 1 1 1 7 12 7 tCLCL 14 tCLCL 28 tCLCL *All internal MOVX operations execute at the 0 Stretch setting. ** Default Stretch setting for external MOVX operations following reset. Stretch Cycle Count MOVX Machine Cycles
RD , WR Pulse Width (in oscillator clocks)
tMCS (4X/ 2X = X CD1:0 = 11) 2048 tCLCL 4096 tCLCL 8192 tCLCL 12288 tCLCL 16384 tCLCL 20480 tCLCL 24576 tCLCL 28672 tCLCL
EXTENDED STACK POINTER
The DS80C390 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the performance of large programs written in high-level languages such as C. The 10-bit stack pointer feature is enabled by setting the Stack Address Mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an 8-bit stack located in the Scratchpad RAM area. When the SA bit is set, the device will address up to 1kB of stack memory in the first 1kB of the internal MOVX memory. The 10-bit stack pointer address is generated by concatenating the lower two bits of the Extended Stack Pointer (ESP;9Bh) and the traditional 8051 Stack Pointer (SP;81h). The 10-bit stack pointer cannot be enabled when the 4kB of SRAM is mapped as both program and data memory.
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ENHANCED DUAL DATA POINTERS
The DS80C390 contains two data pointers, DPTR0 and DPTR1, designed to improve performance in applications that require high data throughput. Incorporating a second data pointer allows the software to greatly speed up block data (MOVX) moves by using one data pointer as a source register and the other as the destination register. DPTR0 is located at the same address as the original 8051 data pointer, allowing the DS80C390 to execute standard 8051 code with no modifications. The second data pointer, DPTR1, is split between the DPH1 and DPL1 SFRs, similar to the DPTR0 configuration. The active data pointer is selected with the data pointer select bit SEL (DPS.0). Any instructions that reference the DPTR (i.e., MOVX A, @DPTR), will select DPTR0 if SEL=0, and DPTR1 if SEL=1. Because the bits adjacent to SEL are not implemented, the state of SEL (and thus the active data pointer) can be quickly toggled by the INC DPS instruction without disturbing other bits in the DPS register. Unlike the standard 8051, the DS80C390 has the ability to decrement as well as increment the data pointers without additional instructions. When the INC DPTR instruction is executed, the active DPTR increments or decrements according to the ID1, ID0 (DPS.7-6), and SEL (DPS.0) bits as shown. The inactive DPTR is not affected.
DATA POINTER AUTOINCREMENT/DECREMENT CONFIGURATION Table 9
ID1 X X 0 1 ID0 0 1 X X SEL 0 0 1 1 Result of INC DPTR Increment DPTR0 Decrement DPTR0 Increment DPTR1 Decrement DPTR1
Another useful feature of the device is its ability to automatically switch the active data pointer after a DPTR-based instruction is executed. This feature can greatly reduce the software overhead associated with data memory block moves, which toggle between the source and destination registers. When the Toggle Select bit (TSL;DPS.5) is set to 1, the SEL bit (DPS.0) is automatically toggled every time one of the following DPTR related instructions is executed. INC DPTR MOV DPTR, #data16 MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A As a brief example, if TSL is set to 1, then both data pointers can be updated with two INC DPTR instructions. Assume that SEL=0, making DPTR the active data pointer. The first INC DPTR increments DPTR and toggles SEL to 1. The second instruction increments DPTR1 and toggles SEL back to 0. INC DPTR INC DPTR
CLOCK CONTROL AND POWER MANAGEMENT
The DS80C390 includes a number of unique features that allow flexibility in selecting system clock sources and operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a clock multiplier is included in the processor's clock circuit. Also, in addition to the standard 16 of 58 110199
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80C32 Idle and power down (Stop) modes, the DS80C390 provides a new Power Management Mode. This mode allows the processor to continue instruction execution, yet at a very low speed to significantly reduce power consumption (below even Idle mode). The DS80C390 also features several enhancements to Stop mode that make this extremely low power mode more useful. Each of these features is discussed in detail below.
SYSTEM CLOCK CONTROL
As mentioned previously, the microcontroller contains special clock control circuitry that simultaneously provides maximum timing flexibility and maximum availability and economy in crystal selection. The logical operation of the system clock divide control function is shown in Figure 2. A 3:1 multiplexer, controlled by CD1, CD0 (PMR.7-6), selects one of three sources for the internal system clock: Crystal oscillator or external clock source (Crystal oscillator or external clock source) divided by 256 (Crystal oscillator or external clock source) frequency multiplied by 2 or 4 times.
SYSTEM CLOCK CONTROL DIAGRAM Figure 2
The system clock control circuitry generates two clock signals that are used by the microcontroller. The internal system clock provides the timebase for timers and internal peripherals. The system clock is run through a divide by 4 circuit to generate the machine cycle clock that provides the timebase for CPU operations. All instructions execute in one to five machine cycles. It is important to note the distinction between these two clock signals, as they are sometimes confused, creating errors in timing calculations. Setting CD1, CD0 to 0 enables the frequency multiplier, either doubling or quadrupling the frequency of the crystal oscillator or external clock source. The 4X/ 2X bit controls the multiplying factor, selecting twice or four times the frequency when set to 0 or 1, respectively. Enabling the frequency multiplier results in apparent instruction execution speeds of 2 or 1 clocks. Regardless of the configuration of the frequency multiplier, the system clock of the microcontroller can never be operated faster than 40 MHz. This means that the maximum crystal oscillator or external clock source is 10 MHz when using the 4X setting, and 20 MHz when using the 2X setting. The primary advantage of the clock multiplier is that it allows the microcontroller to use slower crystals to achieve the same performance level. This reduces EMI and cost, as slower crystals are generally more available and thus less expensive.
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SYSTEM CLOCK CONFIGURATION Table 10
CD1 0 0 0 1 1 CD0 0 0 1 0 1
4X/ 2X
0 1 N/A N/A N/A
Name Frequency Multiplier (2X) Frequency Multiplier (4X) Reserved Divide-by-four (Default) Power Management Mode
Clocks/MC 2 1 4 1024
Max. External Frequency 20 MHz 10 MHz 40 MHz 40 MHz
The system clock and machine cycle rate changes one machine cycle after the instruction changing the control bits. Note that the change will affect all aspects of system operation, including timers and baud rates. The use of the switchback feature, described later, can eliminate many of the problems associated with the Power Management Mode. Changing the system clock/machine cycle clock frequency The microcontroller incorporates a special locking sequence to ensure "glitch-free" switching of the internal clock signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-four) state. For example, to change from 00 (frequency multiplier) to 11 (PMM), the software must change the bits in the following sequence: 00 -> 10 -> 11. Attempts to switch between invalid states will fail, leaving the CD1, CD0 bits unchanged. The following sequence must be followed when switching to the frequency multiplier as the internal time source. This sequence can only be performed when the device is in divide-by-four operation. The steps must be followed in this order, although it is possible to have other instructions between them. Any deviation from this order will cause the CD1, CD0 bits to remain unchanged. Switching from frequency multiplier to non-multiplier mode requires no steps other than the changing of the CD1, CD0 bits. 1. 2. 3. 4. 5. Ensure that the CD1, CD0 bits are set to 10, and the RGMD (EXIF.2) bit = 0. Clear the CTM (Crystal Multiplier Enable) bit. Set the 4X/ 2X bit to the appropriate state. Set the CTM (Crystal Multiplier Enable) bit. Poll the CKRDY bit (EXIF.4), waiting until it is set to 1. This will take approximately 65536 cycles of the external crystal or clock source. 6. Set CD1, CD0 to 00. The frequency multiplier will be engaged on the machine cycle following the write to these bits.
OSCILLATOR FAIL DETECT
The microprocessor contains a safety mechanism called an on-chip Oscillator Fail Detect circuit. When enabled, this circuit causes the processor to be held in reset if the oscillator frequency falls below TBD kHz. In operation, this circuit complements the Watchdog timer. Normally, the watchdog timer is initialized so that it will time-out and will cause a processor reset in the event that the processor loses control. In the event of a crystal or external oscillator failure, however, the watchdog timer will not function and there is the potential for the processor to fail in an uncontrolled state. The use of the oscillator fail detect circuit forces the processor to a known state (i.e., reset) even if the oscillator stops. The oscillator fail detect circuitry is enabled when software sets the enable bit OFDE (PCON.4) to a 1. Please note that software must use a "Timed Access" procedure (described later) to write this bit. The OFDF (PCON.5) bit will also be set to a 1 when the circuitry detects an oscillator failure, and the processor is forced into a reset state. This bit can only be cleared to a 0 by a power fail reset or by software. The oscillator fail detect circuitry will not be activated when the oscillator is stopped due to the processor entering Stop mode. 18 of 58 110199
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POWER MANAGEMENT MODE (PMM)
Crystal Speed 11.0592 MHz 16 MHz 25 MHz 33 MHz 40 MHz Machine Cycle Rate Full Operation PMM (4 clocks per (1024 clocks per machine cycle) machine cycle) 2.765 MHz 10.8 kHz 4.0 MHz 15.6 kHz 6.25 MHz 24.4 kHz 8.25 MHz 32.2 kHz 10.0 MHz 39.1 kHz Operating Current Estimates Full Operation PMM (4 clocks per (1024 clocks per machine cycle) machine cycle) 13.1 ma 4.8 ma 17.2 ma 5.6 ma 25.7 ma 7.0 ma 32.8 ma 8.2 ma TBD TBD
Note that power consumption in PMM is less than Idle mode. While both modes leave the power-hungry internal timers running, PMM runs all clocked functions such as timers at the rate of crystal divided by 1024, rather than crystal divided by 4. Even though instruction execution continues in PMM (albeit at a reduced speed), it still consumes less power than Idle mode. As a result there is little reason to use Idle mode in new designs.
SWITCHBACK
When enabled, the Switchback feature allows serial ports and interrupts to automatically switch back from divide by 1024 (PMM) to divide by 4 (standard speed) operation. This feature makes it very convenient to use the Power Management Mode in real-time applications. Software can simply set the CD1 and CD0 clock control bits to the 4 clocks per cycle mode to exit PMM. However, the microcontroller provides hardware alternatives for automatic Switchback to standard speed (divide by 4) operation. The Switchback feature is enabled by setting the SFR bit SWB (PMR.5) to a 1. Once it is enabled, and when PMM is selected, two possible events can cause an automatic Switchback to divide by four mode. First, if an interrupt occurs and is acknowledged, the system clock will revert from PMM to divide by four mode. For example, if INT0 is enabled and the CPU is not servicing a higher priority interrupt, then Switchback will occur on INT0 . However, if INT0 is not enabled or the CPU is servicing a higher priority interrupt, then activity on INT0 will not cause Switchback to occur. A Switchback can also occur when an enabled UART detects the start bit indicating the beginning of an incoming serial character or when the SBUF register is loaded initiating a serial transmission. Note that a serial character's start bit does not generate an interrupt. The interrupt occurs only on reception of a complete serial word. The automatic Switchback on detection of a start bit allows timer hardware to return to divide by 4 operation (and the correct baud rate) in time for a proper serial reception or transmission. So with Switchback enabled and a serial port enabled, the automatic switch to divide by 4 operation occurs in time to receive or transmit a complete serial character as if nothing special had happened.
STATUS
The Status register (STATUS;C5h) provides information about interrupt and serial port activity to assist in determining if it is possible to enter PMM. The microprocessor supports three levels of interrupt priority: Power-fail, High, and Low. The PIP (Power-fail Priority Interrupt Status; STATUS.7), HIP (High Priority Interrupt Status; STATUS.6), and LIP (Low Priority Interrupt Status; STATUS.5) status bits, when set to a logic one, indicate the corresponding level is in service.
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Software should not rely on a lower-priority level interrupt source to remove PMM (Switchback) when a higher level is in service. Check the current priority service level before entering PMM. If the current service level locks out a desired Switchback source, then it would be advisable to wait until this condition clears before entering PMM. Alternately, software can prevent an undesired exit from PMM by intentionally entering a low priority interrupt service level before entering PMM. This will prevent other low priority interrupts from causing a Switchback. Entering PMM during an ongoing serial port transmission or reception can corrupt the serial port activity. To prevent this, a hardware lockout feature ignores changes to the clock divisor bits while the serial ports are active. Serial port activity can be monitored via the Serial Port Activity bits located in the Status register.
IDLE MODE
Setting the IDLE bit (PCON.0) invokes the Idle mode. Idle will leave internal clocks, serial ports and timers running. Power consumption drops because memory is not being accessed and instructions are not being executed. Since clocks are running, the Idle power consumption is a function of crystal frequency. It should be approximately 1/2 of the operational power at a given frequency. The CPU can exit Idle mode with any interrupt or a reset. Because Power Management Mode (PMM) consumes less power than Idle mode, as well as leaving timers and CPU operating, Idle mode is no longer recommended for new designs, and is included for backward software compatibility only.
STOP MODE
Setting the STOP bit of the Power Control register (PCON.1) invokes Stop mode. Stop mode is the lowest power state (besides power off) since it turns off all internal clocking. The ICC of a standard Stop mode is approximately 1 A (consult the Electrical Specifications section for full details). All processor operation ceases at the end of the instruction that sets the STOP bit. The CPU can exit Stop mode via an external interrupt, if enabled, or a reset condition. Internally generated interrupts (timer, serial port, watchdog) cannot cause an exit from Stop mode because internal clocks are not active in Stop mode.
BAND-GAP SELECT
The DS80C390 provides two enhancements to Stop mode. As described below, the device provides a band-gap reference to determine Power-fail Interrupt and Reset thresholds. The band-gap reference is controlled by the Band-Gap Select bit, BGS (RCON.0). Setting BGS to a 1 will keep the band-gap reference enabled during Stop mode. The default or reset condition of the bit is logic 0, which disables the band-gap during Stop mode. This bit has no control of the reference during full power, PMM, or Idle modes. With the band-gap reference enabled, the Power-fail reset and interrupt are valid means for leaving Stop mode. This allows software to detect and compensate for a power supply sag or brownout, even when in Stop mode. In Stop mode with the band-gap enabled, ICC will be approximately 100 A compared with 1 A with the band-gap disabled. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the band-gap can remain disabled. Only the most power sensitive applications should disable the band-gap reference in Stop mode, as this results in an uncontrolled power down condition.
RING OSCILLATOR
The second enhancement to Stop mode reduces power consumption and allows the device to restart instantly when exiting Stop mode. The ring oscillator is an internal clock that can optionally provide the clock source to the microcontroller when exiting Stop mode in response to an interrupt. 20 of 58 110199
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During Stop mode the crystal oscillator is halted to maximize power savings. Typically 4 - 10 ms are required for an external crystal to begin oscillating again once the device receives the exit stimulus. The ring oscillator, by contrast, is a free-running digital oscillator that has no startup delay. The ring oscillator feature is enabled by setting the Ring Oscillator Select bit, RGSL (EXIF.1). If enabled, the microcontroller uses the ring oscillator as the clock source to exit Stop mode, resuming operation in less than 100 ns. After 65536 oscillations of the external clock source (not the ring oscillator), the device will clear the Ring Oscillator Mode bit, RGMD (EXIF.2) to indicate that the device has switched from the ring oscillator to the external clock source. The ring oscillator runs at approximately 10 MHz, but varies over temperature and voltage. As a result, no serial communication or precision timing should be attempted while running from the ring oscillator since the operating frequency is not precise. The default state exits Stop mode without using the ring oscillator.
TIMED ACCESS PROTECTION
Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write operation. The Timed Access procedure prevents an errant processor from accidentally altering bits that would seriously affect processor operation. The Timed Access procedure requires that the write of a protected bit be immediately preceded by the following two instructions: MOV 0C7h, #0AAh MOV 0C7h, #55h Writing an AAh followed by a 55h to the Timed Access register (location C7h), opens a three-cycle window that allows software to modify one of the protected bits. If the instruction that seeks to modify the protected bit is not immediately preceded by these instructions, the write will be ignored. The protected bits are: WDCON.6 WDCON.3 WDCON.1 WDCON.0 RCON.0 ACON.2 ACON.1-0 MCON.7-6 MCON.5 MCON.3-0 C0C.3 C1C.3 P4CNT.6 P4CNT.5-0 P5CNT.2-0 COR.7 COR.6-5 COR.4-3 COR.2-1 COR.0 POR WDIF EWT RWT BGS SA AM1-AM0 IDM1-IDM0 CMA PDCE3-PDCE.0 CRST CRST SBCAN P5.7-P5.5 IRDACK C1BPR7-C1BPR6 C0BPR7-C0BPR6 COD1-COD0 CLKOE Power-On Reset Flag Watchdog Interrupt Flag Watchdog Reset Enable Reset Watchdog Timer Band-Gap Select Stack Address Mode Address Mode Select bits Internal Memory Configuration and Location bits CAN Data Memory Assignment Program/Data Chip Enables CAN 0 Reset CAN 1 Reset Single Bus CAN Port 4 Pin Configuration Control Bits Configuration Control Bits IRDA Clock Output Enable CAN 1 Baud Rate Pre-scale Bits CAN 0 Baud Rate Pre-scale Bits CAN Clock Output Divide Bit 1 and Bit 0 CAN Clock Output Enable
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EMI REDUCTION
One of the major contributors to radiated noise in an 8051-based system is the toggling of ALE. The microcontroller allows software to disable ALE when not used by setting the ALEOFF (PMR.2) bit to a 1. When ALEOFF = 1, ALE will automatically toggle during an off-chip MOVX. However, ALE will remain static when performing on-chip memory access. The default state of ALEOFF is 0 so ALE normally toggles at a frequency of XTAL/4.
PERIPHERAL OVERVIEW
The DS80C390 provides several of the most commonly needed peripheral functions in microcomputerbased systems. New functions include a second serial port, power-fail reset, power-fail interrupt flag, and a programmable watchdog timer. In addition, the microcontroller contains two Controller Area Network (CAN) modules for industrial communication applications. Each of these peripherals is described below, and more details are available in the User's Guide.
SERIAL PORTS
The microcontroller provides a serial port (UART) that is identical to the 80C52. In addition it includes a second hardware serial port that is a full duplicate of the standard one. This second port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1). It has duplicate control functions included in new SFR locations. The second serial port can alternately be mapped to P5.2 and P5.3 to allow use of both serial ports in nonmultiplexed mode. Both ports can operate simultaneously but can be at different baud rates or even in different modes. The second serial port has similar control registers (SCON1, SBUF1) to the original. The new serial port can only use Timer 1 for baud rate generation. The SCON0 register provides control for serial port 0 while its I/O buffer is SBUF0. The registers SCON1 and SBUF1 provide the same functions for the second serial port. A full description on the use and operation of both serial ports may be found in the User's Guide.
WATCHDOG TIMER
The Watchdog is a free running, programmable timer that can set a flag, cause an interrupt, and/or reset the microcontroller if allowed to reach a preselected time-out. It can be restarted by software. A typical application uses the watchdog timer as a reset source to prevent software from losing control. The watchdog timer is initialized, selecting the time-out period and enabling the reset and/or interrupt functions. After enabling the reset function, software must then restart the timer before its expiration or hardware will reset the CPU. In this way if the code execution goes awry and software does not reset the watchdog as scheduled, the processor is put in a known good state: reset. Software can select one of four time-out values as controlled by the WD1 and WD0 bits. Time-out values are precise since they are a function of the crystal frequency. When the Watchdog times out, it sets the Watchdog Timer Reset Flag (WTRF=WDCON.2) which generates a reset if enabled by the Enable Watchdog Timer Reset (EWT=WDCON.1) bit. Both the Enable Watchdog Timer Reset and the Reset Watchdog Timer control bits are protected by Timed Access circuitry. This prevents errant software from accidentally clearing or disabling the Watchdog. The Watchdog interrupt is useful for systems that do not require a reset circuit. It will set the WDIF (Watchdog interrupt) flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source, which is independent of the watchdog reset function. The interrupt is common used 22 of 58 110199
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during the debug process to determine where watchdog reset commands must be located in the application software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor from power saving modes. The Watchdog timer is controlled by the Clock Control (CKCON) and the Watchdog Control (WDCON) SFRs. CKCON.7 and CKCON.6 are WD1 and WD0 respectively, and they select the Watchdog time-out period. Of course, the 4X/ 2X (PMR.3) and CD1 :0 (PMR.7:6) system clock control bits also affect the time-out period. Selection of time-out is shown below.
WATCHDOG TIME-OUT VALUES Table 11
4X/ 2X 1 0 x x x
CD1:0 00 00 01 10 11 WATCHDOG INTERRUPT TIME-OUT WATCHDOG RESET TIME-OUT WD1:0=00 WD1:0=01 WD1:0=10 WD1:0=11 WD1:0=00 WD1:0=01 WD1:0=10 WD1:0=11 215 216 217 217 225 218 219 220 220 228 221 222 223 223 231 224 225 226 226 234 215 +512 216 +512 217 +512 217 +512 225 +512 218 +512 219 +512 220 +512 220 +512 228 +512 221 +512 222 +512 223 +512 223 +512 231 +512 224 +512 225 +512 226 +512 226 +512 234 +512
The table demonstrates that for a 33 MHz crystal frequency the Watchdog timer is capable of producing time-out periods from 3.97 ms (217 * 1/33 MHz) to over two seconds (2.034 = 226 * 1/33 MHz) with the default setting of CD1 :0 (=10). This wide variation in time-out periods allows very flexible system implementation. In a typical initialization, the user selects one of the possible counter values to determine the time-out. Once the counter chain has completed a full count, hardware will set the interrupt flag (WDIF=WDCON.3). Regardless of whether the software makes use of this flag, there are then 512 clocks left until the reset flag (WTRF=WDCON.2) is set. Software can enable (1) or disable (0) the reset using the Enable Watchdog Timer Reset (EWT=WDCON.1) bit.
POWER FAIL RESET
The microcontroller incorporates an internal precision band-gap voltage reference and comparator circuit which provide a power-on and power-fail reset function. This circuit monitors the processor's incoming power supply voltage (VCC), and holds the processor in reset while V is below the minimum voltage CC level. When power exceeds the reset threshold, a full power-on reset will be performed. In this way, this internal voltage monitoring circuitry handles both power-up and power-down conditions without the need for additional external components. Once VCC has risen above VRST , the device will automatically restart the oscillator for the external crystal and count 65,536 clock cycles before program execution begins at location 0000h. This helps the system maintain reliable operation by only permitting processor operation when the supply voltage is in a known good state. Software can determine that a power-on reset has occurred by checking the Power-On Reset flag (POR;WDCON.6). Software should clear the POR bit after reading it.
POWER FAIL INTERRUPT
The band-gap voltage reference that sets a precise reset threshold also generates an optional early warning Power-fail Interrupt (PFI). When enabled by software, the processor will vector to ROM address 0033h if VCC drops below VPFW . PFI has the highest priority. The PFI enable is in the Watchdog Control SFR (EPFI;WDCON.5). Setting this bit to logic 1 will enable the PFI. Application software can also read the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the interrupt enable and must be cleared by software. 23 of 58 110199
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EXTERNAL RESET PINS
The DS80C390 has both reset input (RST) and reset output ( RSTOL ) pins. The RSTOL pin supplies an active low Reset when the microprocessor is issued a Reset from either a high on the RST pin, a time out of the watchdog timer, a crystal oscillator fail, or an internally detected power-fail. The timing of the RSTOL pin is dependent on the source of the reset. Reset Type/Source Power-on reset External reset Power fail Watchdog timer reset Oscillator fail detect
RSTOL Duration 65536 tCLCL (as described in Power Cycle Timing Characteristics) < 1.25 machine cycles 65536 tCLCL (as described in Power Cycle Timing Characteristics) 2 machine cycles 65536 tCLCL (as described in Power Cycle Timing Characteristics)
INTERRUPTS
The microcontroller provides 16 interrupt sources with three priority levels. All interrupts, with the exception of the Power Fail interrupt, are controlled by a series combination of individual enable bits and a global interrupt enable EA (IE.7). Setting EA to a 1 allows individual interrupts to be enabled. Clearing EA disables all interrupts regardless of their individual enable settings. The three available priority levels are low, high, and highest. The highest priority level is reserved for the Power Fail Interrupt only. All other interrupt priority levels have individual priority bits that when set to a 1 establish the particular interrupt as high priority. In addition to the user-selectable priorities, each interrupt also has an inherent natural priority, used to determine the priority of simultaneously occurring interrupts. The available interrupt sources, their flags, their enables, their natural priority, and their available priority selection bits are identified in the following table.
INTERRUPT SUMMARY Table 12
NAME PFI INT0 TF0 INT1 TF1 SCON0 TF2 SCON1 INT2 INT3 INT4 INT5 C0I C1I WDTI CANBUS DESCRIPTION Power Fail Interrupt External Interrupt 0 Timer 0 External Interrupt 1 Timer 1 TI0 or RI0 from serial port 0 Timer 2 TI1 or RI1 from serial port 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 CAN0 Interrupt CAN1 Interrupt Watchdog Timer CAN0/1 Bus Activity VECTOR NATURAL PRIORITY 33h 0 03h 1 0Bh 2 13h 3 1Bh 4 23h 5 2Bh 3Bh 43h 4Bh 53h 5Bh 6Bh 73h 63h 7Bh 6 7 8 9 10 11 12 13 14 15 FLAG BIT PFI(WDCON.4) IE0(TCON.1)** TF0(TCON.5)* IE1(TCON.3)** TF1(TCON.7)* RI_0(SCON0.0) TI_0(SCON0.1) TF2(T2CON.7) ET2(IE.5) RI_1(SCON1.0) ES1(IE.6) TI_1(SCON1.1) IE2 (EXIF.4) EX2 (EIE.0) IE3 (EXIF.5) EX3 (EIE.1) IE4 (EXIF.6) EX4 (EIE.2) IE5 (EXIF.7) EX5 (EIE.3) various C0IE (EIE.6) various C1IE (EIE.5) WDIF (WDCON.3) EWDI (EIE.4) various CANBIE (EIE.7) PRIORITY CONTROL BIT EPFI(WDCON.5) N/A EX0(IE.0) PX0(IP.0) ET0(IE.1) PT0(IP.1) EX1(IE.2) PX1(IP.2) ET1(IE.3) PT1(IP.3) ES0(IE.4) PS0(IP.4) PT2(IP.7) PS1(IP.6) PX2 (EIP.0) PX3 (EIP.1) PX4 (EIP.2) PX5 (EIP.3) C0IP (EIP.6) C1IP (EIP.5) PWDI (EIP.4) CANBIP (EIP.7) ENABLE BIT
Unless marked, all flags must be cleared by the application software. * Cleared automatically by hardware when the service routine is entered. ** If edge triggered, flag is cleared automatically by hardware when the service routine is entered. If level triggered, flag follows the state of the interrupt pin. 24 of 58 110199
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CONTROLLER AREA NETWORK (CAN) MODULE
The DS80C390 incorporates two CAN controllers that are fully compliant with the CAN 2.0B specification. CAN is a highly robust, high-performance communication protocol for serial communications. Popular in a wide range of applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware. The CAN controllers support the use of 11-bit standard or 29-bit extended acceptance identifiers for up to 15 messages, with the standard 8 byte data field, in each message. Fourteen of the fifteen message centers are programmable in either transmit or receive modes, with the fifteenth designated as a FIFObuffered, receive-only message center to help prevent data overruns. All message centers support two separate 8-bit media masks and media arbitration fields for incoming message verification. This feature supports the use of higher level protocols which make use of the first and/or second byte of data as a part of the acceptance layer for storing incoming messages. Each message center can also be programmed independently to test incoming data with or without the use of the global masks. Global controls and status registers in each CAN unit allow the microcontroller to evaluate error messages, generate interrupts, locate and validate new data, establish the CAN Bus timing, establish identification mask bits, and verify the source of individual messages. Each message center is individually equipped with the necessary status and control bits to establish direction, identification mode (standard or extended), data field size, data status, automatic remote frame request and acknowledgment, and perform masked or non-masked identification acceptance testing.
COMMUNICATING WITH THE CAN MODULE
The microcontroller interface to the CAN modules is divided into two groups of registers. All of the global CAN status and control bits as well as the individual message center control/status registers are located in the Special Function Register map. The remaining registers associated with the message centers (data identification, identification/arbitration masks, format and data) are located in MOVX data space. The CMA bit (MCON.5) allows the message centers to be mapped to either 00EE00h-00EEFFh (CMA=0 or 401000h-4011FFh (CMA=1), reducing the possibility of a memory conflict with application software. Note that setting the CMA bit employs a special twenty-third address bit that is only used for addressing CAN MOVX memory. The internal architecture of the DS80C390 requires that the device be in one of the two 22-bit addressing modes when the CMA bit is set to correctly utilize the twenty-third bit and access the CAN MOVX memory. A special lockout feature prevents the accidental software corruption of the control, status and mask registers while a CAN operation is in progress. Each CAN processor utilizes a total of 15 message centers. Each message center is composed of four specific areas. These include: 1. Four arbitration registers (C0MxAR0-3 and C1MxAR0-3) which store either the 11-bit or 29-bit arbitration value. These registers are located in the MOVX memory map. 2. A Format Register (C0MxF and C1MxF) which informs the CAN processor as to the direction (transmit or receive), the number of data bytes in the message, the Identification Format (standard or extended), and the optional use of the Identification Mask or Media Mask during message evaluation. This register is located in the MOVX memory map. 3. Eight data bytes for storage of 0 - 8 bytes of data (C0MxD0-7 and C1MxD0-7) are located in the MOVX memory map. 4. Message Control Registers (C0MxC and C1MxC) are located in the SFR memory for fast access.
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Each of the message centers is identical with the exception of message center 15. Message center 15 has been designed as a receive only center and is also buffered through the use of a two message FIFO to help prevent message loss in a message overrun situation. The receipt of a third message before either of the first two are read will overwrite the second message, leaving the first message undisturbed. Modification of the CAN registers located in MOVX memory is protected via the SWINT bits, with one bit protecting each respective CAN module. Consult the description of this bit in the User's Guide for more information. Each CAN Module contains a block of Control/Status/Mask registers, 14 functionally identical message centers, plus a fifteenth message center which is receive only and incorporates a buffered FIFO. The following tables describe the organization of the message centers located in MOVX space.
MOVX MESSAGE CENTERS FOR CAN 0
CAN 0 CONTROL/STATUS/MASK REGISTERS Register C0MID0 C0MA0 C0MID1 C0MA1 C0BT0 C0BT1 C0SGM0 C0SGM1 C0EGM0 C0EGM1 C0EGM2 C0EGM3 C0M15M0 C0M15M1 C0M15M2 C0M15M3 7 MID07 M0AA7 MID17 M1AA7 SJW1 SMP ID28 ID20 ID28 ID20 ID12 ID4 ID28 ID20 ID12 ID4 6 MID06 M0AA6 MID16 M1AA6 SJW0 TSEG26 ID27 ID19 ID27 ID19 ID11 ID3 ID27 ID19 ID11 ID3 5 MID05 M0AA5 MID15 M1AA5 BPR5 TSEG25 ID26 ID18 ID26 ID18 ID10 ID2 ID26 ID18 ID10 ID2 4 MID04 M0AA4 MID14 M1AA4 BPR4 TSEG24 ID25 0 ID25 ID17 ID9 ID1 ID25 ID17 ID9 ID1 3 MID03 M0AA3 MID13 M1AA3 BPR3 TSEG13 ID24 0 ID24 ID16 ID8 ID0 ID24 ID16 ID8 ID0 2 MID02 M0AA2 MID12 M1AA2 BPR2 TSEG12 ID23 0 ID23 ID15 ID7 0 ID23 ID15 ID7 0 1 MID01 M0AA1 MID11 M1AA1 BPR1 TSEG11 ID22 0 ID22 ID14 ID6 0 ID22 ID14 ID6 0 0 MID00 M0AA0 MID10 M1AA0 BPR0 TSEG10 ID21 0 ID21 ID13 ID5 0 ID21 ID13 ID5 0 MOVX Data Address1 xxxx00h xxxx01h xxxx02h xxxx03h xxxx04h xxxx05h xxxx06h xxxx07h xxxx08h xxxx09h xxxx0Ah xxxx0Bh xxxx0Ch xxxx0Dh xxxx0Eh xxxx0Fh
CAN 0 MESSAGE CENTER 1
Reserved C0M1AR0 CAN 0 MESSAGE 1 ARBITRATION REGISTER 0 C0M1AR1 CAN 0 MESSAGE 1 ARBITRATION REGISTER 1 C0M1AR2 CAN 0 MESSAGE 1 ARBITRATION REGISTER 2 C0M1AR3 CAN 0 MESSAGE 1 ARBITRATION REGISTER 3 WTOE C0M1F DTBYC3 DTBYC2 DTBYC1 DTBYC0 T/ R MEME MDME EX/ ST C0M1D0-7 CAN 0 MESSAGE 1 DATA BYTES 0 - 7 Reserved xxxx10h - 11h xxxx12h xxxx13h xxxx14h xxxx15h xxxx16h xxxx17h - 1Eh xxxx1Fh
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CAN 0 MESSAGE CENTERS 2-14
MESSAGE CENTER 2 REGISTERS (similar to Message Center 1) MESSAGE CENTER 3 REGISTERS (similar to Message Center 1) MESSAGE CENTER 4 REGISTERS (similar to Message Center 1) MESSAGE CENTER 5 REGISTERS (similar to Message Center 1) MESSAGE CENTER 6 REGISTERS (similar to Message Center 1) MESSAGE CENTER 7 REGISTERS (similar to Message Center 1) MESSAGE CENTER 8 REGISTERS (similar to Message Center 1) MESSAGE CENTER 9 REGISTERS (similar to Message Center 1) MESSAGE CENTER 10 REGISTERS (similar to Message Center 1) MESSAGE CENTER 11 REGISTERS (similar to Message Center 1) MESSAGE CENTER 12 REGISTERS (similar to Message Center 1) MESSAGE CENTER 13 REGISTERS (similar to Message Center 1) MESSAGE CENTER 14 REGISTERS (similar to Message Center 1) CAN 0 MESSAGE CENTER 15
Reserved C0M15AR0 CAN 0 MESSAGE 15 ARBITRATION REGISTER 0 C0M15AR1 CAN 0 MESSAGE 15 ARBITRATION REGISTER 1 C0M15AR2 CAN 0 MESSAGE 15 ARBITRATION REGISTER 2 C0M15AR3 CAN 0 MESSAGE 15 ARBITRATION REGISTER 3 WTOE C0M15F DTBYC3DTBYC2DTBYC1 DTBYC0 0 EX/ ST MEME MDME C0M15D0CAN 0 MESSAGE 15 DATA BYTE 0 - 7 C0M15D7 Reserved xxxxF0h - F1h xxxxF2h xxxxF3h xxxxF4h xxxxF5h xxxxF6h xxxxF7h - FEh xxxxFFh
xxxx20h - 2Fh xxxx30h - 3Fh xxxx40h - 4Fh xxxx50h - 5Fh xxxx60h - 6Fh xxxx70h - 7Fh xxxx80h - 8Fh xxxx90h - 9Fh xxxxA0h - AFh xxxxB0h - BFh xxxxC0h - CFh xxxxD0h - DFh xxxxE0h - EFh
Notes: 1 The first two bytes of the CAN 0 MOVX memory address are dependent on the setting of the CMA bit (MCON.5) CMA=0, xxxx=00EE; CMA=1, xxxx=4010.
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MOVX MESSAGE CENTERS FOR CAN 1
CAN 1 CONTROL/STATUS/MASK REGISTERS
Register 7 6 5 4 3 2 1 0
MOVX Data Address1
C1MID0 C1MA0 C1MID1 C1MA1 C1BT0 C1BT1 C1SGM0 C1SGM1 C1EGM0 C1EGM1 C1EGM2 C1EGM3 C1M15M0 C1M15M1 C1M15M2 C1M15M3
MID07 M0AA7 MID17 M1AA7 SJW1 SMP ID28 ID20 ID28 ID20 ID12 ID4 ID28 ID20 ID12 ID4
MID06 M0AA6 MID16 M1AA6 SJW0 TSEG26 ID27 ID19 ID27 ID19 ID11 ID3 ID27 ID19 ID11 ID3
MID05 M0AA5 MID15 M1AA5 BPR5 TSEG25 ID26 ID18 ID26 ID18 ID10 ID2 ID26 ID18 ID10 ID2
MID04 M0AA4 MID14 M1AA4 BPR4 TSEG24 ID25 0 ID25 ID17 ID9 ID1 ID25 ID17 ID9 ID1
MID03 M0AA3 MID13 M1AA3 BPR3 TSEG13 ID24 0 ID24 ID16 ID8 ID0 ID24 ID16 ID8 ID0
MID02 M0AA2 MID12 M1AA2 BPR2 TSEG12 ID23 0 ID23 ID15 ID7 0 ID23 ID15 ID7 0
MID01 M0AA1 MID11 M1AA1 BPR1 TSEG11 ID22 0 ID22 ID14 ID6 0 ID22 ID14 ID6 0
MID00 M0AA0 MID10 M1AA0 BPR0 TSEG10 ID21 0 ID21 ID13 ID5 0 ID21 ID13 ID5 0
xxxx00h xxxx01h xxxx02h xxxx03h xxxx04h xxxx05h xxxx06h xxxx07h xxxx08h xxxx09h xxxx0Ah xxxx0Bh xxxx0Ch xxxx0Dh xxxx0Eh xxxx0Fh
CAN 1 MESSAGE CENTER 1
Reserved C1M1AR0 CAN 1 MESSAGE 1 ARBITRATION REGISTER 0 C1M1AR1 CAN 1 MESSAGE 1 ARBITRATION REGISTER 1 C1M1AR2 CAN 1 MESSAGE 1 ARBITRATION REGISTER 2 C1M1AR3 CAN 1 MESSAGE 1 ARBITRATION REGISTER 3 WTOE C1M1F DTBYC3 DTBYC2 DTBYC1 DTBYC0 T/ R MEME MDME EX/ ST C1M1D0-7 CAN 1 MESSAGE 1 DATA BYTES 0 - 7 Reserved xxxx10h - 11h xxxx12h xxxx13h xxxx14h xxxx15h xxxx16h xxxx17h - 1Eh xxxx1Fh
CAN 1 MESSAGE CENTERS 2-14 MESSAGE CENTER 2 REGISTERS (similar to Message Center 1) MESSAGE CENTER 3 REGISTERS (similar to Message Center 1) MESSAGE CENTER 4 REGISTERS (similar to Message Center 1) MESSAGE CENTER 5 REGISTERS (similar to Message Center 1) MESSAGE CENTER 6 REGISTERS (similar to Message Center 1) MESSAGE CENTER 7 REGISTERS (similar to Message Center 1) MESSAGE CENTER 8 REGISTERS (similar to Message Center 1) MESSAGE CENTER 9 REGISTERS (similar to Message Center 1) MESSAGE CENTER 10 REGISTERS (similar to Message Center 1) MESSAGE CENTER 11 REGISTERS (similar to Message Center 1) MESSAGE CENTER 12 REGISTERS (similar to Message Center 1) MESSAGE CENTER 13 REGISTERS (similar to Message Center 1) MESSAGE CENTER 14 REGISTERS (similar to Message Center 1)
xxxx20h - 2Fh xxxx30h - 3Fh xxxx40h - 4Fh xxxx50h - 5Fh xxxx60h - 6Fh xxxx70h - 7Fh xxxx80h - 8Fh xxxx90h - 9Fh xxxxA0h - AFh xxxxB0h - BFh xxxxC0h - CFh xxxxD0h - DFh xxxxE0h - EFh
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CAN 1 MESSAGE CENTER 15
C1M15AR0 C1M15AR1 C1M15AR2 C1M15AR3 Reserved CAN 1 MESSAGE 15 ARBITRATION REGISTER 0 CAN 1 MESSAGE 15 ARBITRATION REGISTER 1 CAN 1 MESSAGE 15 ARBITRATION REGISTER 2 CAN 1 MESSAGE 15 ARBITRATION REGISTER 3 xxxxF0h - F1h xxxxF2h xxxxF3h xxxxF4h xxxxF5h xxxxF6h xxxxF7h - FEh xxxxFFh
WTOE MDME
C1M15F DTBYC3 DTBYC2 DTBYC1 DTBYC0 0 EX/ ST MEME C1M15D0CAN 1 MESSAGE 15 DATA BYTE 0 - 7 C1M15D7 Reserved
Notes: 1 The first two bytes of the CAN 1 MOVX memory address are dependent on the setting of the CMA bit (MCON.5) CMA=0, xxxx=00EF; CMA=1, xxxx=4011.
CAN INTERRUPTS
The DS80C390 supports 3 interrupts associated with the CAN controllers. One interrupt is dedicated to each CAN controller, providing receive/transmit acknowledgments from each of its 15 message centers. The remaining interrupt, the Can Bus Activity Interrupt, is used to detect CAN bus activity on the C0RX or C1RX pins. The message center interrupts are enabled/disabled by individual ETI (transmit) and ERI (receive) enable bits in the corresponding Message Control Register (located in SFR memory) for each message center. All of the message center interrupts of each CAN module are ORed together into their respective CAN interrupt. The successful transmission or receipt of a message will set the INTRQ bit in the corresponding Message Control Register (located in SFR memory). This bit can only be cleared via software. In addition, the Global Interrupt Enable bit (IE.7) and the specific CAN Interrupt Enable bit, EIE.6 (CAN0) or EIE.5 (CAN1) must be correctly set to acknowledge a message center interrupt. Interrupt assertion of error and status conditions associated with the CAN modules is controlled by the ERIE and STIE bits located in the CAN Control registers, C0C and C1C.
ARBITRATION AND MASKING
After a CAN module has ascertained that an incoming message is bit error-free, the identification field of that message is then compared against one or more arbitration values to determine if they will be loaded into a message center. Each enabled message center (see the MSRDY bit in the CAN Message Control Register) is tested in order from 1-15. The first message center to successfully pass the test will receive the incoming message and end the testing. The use of masking registers allows the use of more complex identification schemes, as tests can be made based on bit patterns rather than an exact match between all bits in the identification field and arbitration values. Each CAN processor also incorporates a set of five masks to allow messages with different IDs to be grouped and successfully loaded into a message center; Note that some of these masks are optional as per the bits shown in the Arbitration/Masking Feature Summary table. There are several possible arbitration tests, varying according to which message center is involved. If all of the enabled tests succeed, the message is loaded into the respective message center. The most basic test, performed on all messages, compares either 11 (CAN 2.0A) or 29 (CAN 2.0B) bits of the identification field to the appropriate arbitration register, based on the EX/ ST bit in the CAN 0/1 Format Register. The MEME bit (C0MxF.1 or C1MxF.1) controls whether the arbitration and ID registers are 29 of 58 110199
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compared directly or via a mask register. A special set of arbitration registers dedicated to Message center 15 allow added flexibility in filtering this location. If desired, further arbitration can be performed by comparing the first two bytes of the data field in each message against two 8-bit Media Arbitration register bytes. The MDME bit in the CAN Message Center Format Registers (C0MxF.0 or C1MxF.0) either disables (MDME=0) arbitration, or enables (MDME=1) arbitration using the Media ID Mask Registers 0-1. If the 11-bit or 29-bit arbitration and the optional Media Byte arbitration are successful the message is loaded into the respective message center. The Format Register also allows the microcontroller to program each message center to function in a receive or transmit mode via the T/ R bit and to use from 0 to 8 data bytes within the data field of a message. Note that Message Center 15 can only be used in a receive mode. To avoid a priority inversion the DS80C390 CAN processors are configured to reload the transmit buffer with the message of the highest priority (lowest message center number) whenever an arbitration is lost or an error condition occurs.
ARBITRATION/MASKING FEATURE SUMMARY Table 13
Test Name Arbitration Registers Message Center Arbitration Registers 0-1 (Located in each Message Center, MOVX memory) Standard 11-bit arbitration (CAN 2.0A) Mask Registers Standard Global Mask Registers 0-1 (Located in each CAN Control/Status/Mask Register bank, MOVX memory) Extended Global Mask Registers 0-3 (Located in each CAN Control/Status/Mask Register bank, MOVX memory) Media ID Mask Registers 0-1 (Located in each CAN Control/Status/Mask Register bank, MOVX memory) Message Center 15 Mask Registers 0-1 (Located in each CAN Control/Status/Mask Register bank, MOVX memory) Message Center 15 Mask Registers 0-3 (Located in each CAN Control/Status/Mask Register bank, MOVX memory) Control bits and conditions EX/ ST =0 MEME=0: Mask register ignored. ID and arbitration register must match exactly. MEME=1: Only bits corresponding to 1 in mask register are compared in ID and arbitration registers. EX/ ST =1 MEME=0: Mask register ignored. ID and arbitration register must match exactly. MEME=1: Only bits corresponding to 1 in mask register are compared in ID and arbitration registers. MDME=0: Media byte arbitration disabled. MDME =1: Only bits corresponding to 1 in Media ID mask register are compared between data bytes 1 and 2 and Media arbitration registers. EX/ ST =0 MEME=0: Mask register ignored. ID and arbitration register must match exactly. MEME=1: Message center 15 mask registers are ANDed with Global Mask register. Only bits corresponding to 1 in resulting value are compared in ID and arbitration registers. EX/ ST =1 MEME=0: Mask register ignored. ID and arbitration register must match exactly. MEME=1: Message center 15 mask registers are ANDed with Global Mask register. Only bits corresponding to 1 in resulting value are compared in ID and arbitration registers.
Extended 29-bit arbitration (CAN 2.0B)
Message Center Arbitration Registers 0-3 (Located in each Message Center, MOVX memory) Media Arbitration Registers 0-3 (Located in each CAN Control/Status/Mask Register bank, MOVX memory) Message Center 15 Arbitration Registers 0-1 (Located in Message Center 15, MOVX memory)
Media byte arbitration
Message Center 15, Standard 11-bit arbitration (CAN 2.0A)
Message Center 15, Extended 29-bit arbitration (CAN 2.0B)
Message Center 15 Arbitration Registers 0-3 (Located in Message Center 15, MOVX memory)
MESSAGE BUFFERING/OVERWRITE
If a message center is configured for reception (T/ R =0) and the previous message has not been read (DTUP=1), then the disposition of an incoming message to that message center will be controlled by the WTOE bit (located in CAN Arbitration Register 3 of each message center). When WTOE=0, the incoming message will be discarded and the current message untouched. 30 of 58 110199
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If the WTOE bit is set, the incoming message will be received and written over the existing data bytes in that message center. The Receiver Overwrite bit (ROW) will also be set in the corresponding Message Center Control Register, located in SFR memory. Message center 15 is unique in that it incorporates a buffer that can receive up to two messages without loss. If a message is received by message center 15 while it contains an unread message, the new incoming message is held in an internal buffer. When the CAN processor reads the message center 15 memory location and then clears DTUP=INTRQ=EXTRQ=0, the contents of the internal buffer will automatically be loaded into the message center 15 MOVX memory location. The message center 15 WTOE bit controls what happens if a third message is received when both the message center 15 MOVX memory location and the buffer contain unread messages. If WTOE=0, the new message will be discarded, leaving the message center 15 MOVX memory location and the buffer untouched. If WTOE=1, then the third message will write over the buffered message but leave the message center 15 MOVX memory location untouched.
ERROR COUNTER INTERRUPT GENERATION
Each CAN module can be independently configured to alert the microprocessor when either 96 or 128 errors have been detected by the transmit or receive error counters. The Error Count Select bit, ERCS (C0C.1 or C1C.1) selects whether the limit is 96 (ERCS=0) or 128 (ERCS=1) errors. When the error limit is exceeded, the CAN Error Count Exceeded bit, CECE (C0S.6 or C1S.6) bit is set. If the ERIE, C0IE (or C1IE), and EA SFR bits are configured, an interrupt will be generated. If the ERCS bit is set, the device will generate an interrupt when the CECE bit is set or cleared, if the interrupt is enabled.
BIT TIMING
Bit timing of the CAN transmission can be adjusted per the CAN 2.0B specification. The CAN 0/1 Bus Timing Register Zero (C0BT0 and C1BT0), located in the Control/Status/Mask Register block in MOVX memory, controls the PHASE_SEG1 and PHASE_SEG2 time segments as well as the Baud Rate Prescaler (BPR5 - BPR0). The CAN 0/1 Bus Timing Register One (C0BT1 and C1BT1) contains the controls for the sampling rate and the number of clock cycles assigned to the Phase Segment 1 and 2 portions of the Nominal Bit Time. The values of both of the Bus Timing registers are automatically loaded into the CAN Processor following each software change of the SWINT bit from a 1 to a 0 by the microcontroller. The bit timing parameters must be set before starting operation of the CAN Processor. These registers are only modifiable during a software initialization, (SWINT = 1), when the CAN Processor is NOT in a bus off mode, and after the removal of a system reset or a CAN reset. To avoid unpredictable behavior of the CAN Processor, the software cannot clear the SWINT bit when TSEG1 and TSEG2 are both cleared to 0.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Voltage on VCC relative to ground Operating Temperature Storage Temperature Soldering Temperature -0.3 V to (VCC + 0.5 V) -0.3 V to 6.0 V -40 C to +85 C -55 C to +125 C 160 C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL Supply Voltage VCC Power Fail Warning VPFW Min. Operating Voltage VRST Supply Current Active Mode ICC Supply Current Idle Mode IIDLE Supply Current Stop Mode ISTOP Supply Current Stop Mode, ISPBG Band-gap enabled Input Low Level VIL Input High Level VIH Input High Level for XTAL1, VIH2 RST Output Low Voltage for Port 1, VOL1 3, 4, 5 @ IOL=1.6 mA Output Low Voltage for Port 0, VOL2 1, 2, 4, PCE0 - 3 , RD , WR , RSTOL , PSEN , and ALE, @ IOL=3.2 mA Output High Voltage for Port VOH1 1,3,4,5, @ IOH= -50 A Output High Voltage for Port VOH2 1,3,4,5 @ IOH= -1.5 mA Output High Voltage for Port VOH3 0,1,2,4, PCE0 - 3 , RSTOL , PSEN , RD , WR , and ALE @ IOH= -8 mA Input Low Current for Port 1, IIL 3, 4, 5 @0.45V Logic 1 to 0 Transition Current IT1 for Port 1, 3, 4, 5 Input Leakage Current for Port IL 0 (input mode only) RST Pulldown Resistance RRST MIN VRST 4.25 4.0 TYP 5.0 4.38 4.13 35 15 1 200 MAX 5.5 4.5 4.25 UNITS V
V
NOTES
V mA mA A A V V V V V
1 2 3 3
-0.5 2.0 3.5
+0.8 VCC +0.5 VCC +0.5 0.45 0.45
10 4
2.4 2.4 2.4
V V V
10 5 4
-55 -650 -300 50 32 of 58 +300 170
A A A k
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NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. Active current measured with 40 MHz clock source on XTAL1, VCC=RST= 5.5 V, all other pins disconnected. 2. Idle mode current measured with 40 MHz clock source on XTAL1, VCC= 5.5 V, RST= EA =VSS, all other pins disconnected. 3. Stop mode current measured with XTAL1 = RST = EA = VSS, VCC= 5.5 V, all other pins disconnected. This value is not guaranteed. Users who are sensitive to this specification should contact Dallas Semiconductor for more information. 4. When these pins are used to address external memory or as CAN interface signals. 5. This measurement reflects the port during a 0 to 1 transition in I/O mode. During this period a oneshot circuit drives the ports hard for two clock cycles. 6. Port 3 pins 3.6 and 3.7 will have a stronger than normal pullup drive for one oscillator period following the transition of either the RD or WR from a 0 to 1 transition. 7. This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also have to overcome the transition current. 8. Ports 1(in I/O mode), 3, 4, and 5 source transition current when being pulled down externally. It reaches its maximum at approximately 2V. 9. During the external addressing mode, weak latches maintain the previously driven value from the processor on Port 0 until such time that Port 0 is driven by external memory source; and on Port 1, 2 and 4 for one XTAL1 cycle prior to change in output address from Port 1, 2 and 4. 10. RST= VCC. This condition mimics operation of pins in I/O mode.
TYPICAL ICC VERSUS FREQUENCY
35 ICC mA 30 25 20 15 5 3 2 024 12 33 40 MHz XTAL FREQUENCY
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AC ELECTRICAL CHARACTERISTICS (Multiplexed address/data bus)
40 MHz PARAMETER SYMBOL MIN MAX Oscillator Freq. (Ext. Osc) 1 / tCLCL 0 40 (Ext. Crystal) 1 40 ALE Pulse Width tLHLL Port 0 Instruction Address or tAVLL CE0 - 4 Valid to ALE Low Address Hold after ALE Low tLLAX1 ALE Low to Valid Instruction In tLLIV tLLPL ALE Low to PSEN Low tPLPH PSEN Pulse Width tPLIV PSEN Low to Valid Instruction In tPXIX 0 Input Instruction Hold after PSEN tPXIZ Input Instruction Float after PSEN Port 0 Address to Valid Instruction tAVIV1 In Port 2, 4 Address to Valid tAVIV2 Instruction In tPLAZ 0 PSEN Low to Address Float VARIABLE CLOCK MIN MAX 0 40 1 40 0.375 tMCS - 5 0.125 tMCS - 5 0.125 tMCS - 5 0.625 tMCS - 20 0.125 tMCS - 5 0.5 tMCS - 5 0.5 tMCS - 20 0 0.25 tMCS - 5 0.75 tMCS - 20 0.875 tMCS - 25 0 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
1. All parameters apply to both commercial and industrial temperature operation unless otherwise noted. 2. The value tM CS is a function of the machine cycle clock in terms of the processor's input clock frequency. These relationships are described in the "Stretch Value Timing" table. 3. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN , RD and WR with 100 pF. 4. Interfacing to memory devices with float times (turn off times) over 25 ns may cause bus contention. This will not damage the parts, but will cause an increase in operating current. 5. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle variation. 6. Some AC timing characteristic drawings contain references to the CLK signal. This waveform is provided to assist in determining the relative occurrence of events, and cannot be used to determine the timing of signals relative to the external clock.
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MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE
MOVX CHARACTERISTICS (Multiplexed address/data bus)
PARAMETER SYMBOL MIN UNITS STRETCH VALUES CST (MD2:0) ns CST = 0 1 CST 3 ns 4 CST 7 ns CST = 0 1 CST 3 4 CST 7 ns 0 CST 3 ns 4 CST 7 ns CST =0 1 CST 7 ns CST =0 1 CST 7 0.5 tMCS -20 ns CST =0 CST *tMCS -20 1 CST 7 ns 0.25 tMCS -5 ns CST = 0 0.5tMCS -5 1 CST 3 1.5 tMCS -5 4 CST 7 0.625 tMCS -20 ns CST = 0 (C ST +0.25)*tMCS -40 1 CST 3 (C ST +1.25)*tMCS -40 4 CST 7 MAX
MOVX ALE Pulse Width
tLHLL2
Port 0 MOVX Address, CE0 - 4 , PCE0- 4 Valid to ALE Low Address Hold after MOVX Read/Write
RD
tAVLL2
tLLAX2 tRLRH tWLWH tRLDV tRHDX tRHDZ
Pulse Width
WR Pulse Width
RD
0.375 tMCS -5 0.5 tMCS -5 1.5 tMCS -10 0.125 tMCS -5 0.25tMCS -5 1.25 tMCS -10 0.125 tMCS -5 1.125 tMCS -5 0.5 tMCS -5 CST *tMCS -10 0.5 tMCS -5 CST *tMCS -10
Low to Valid Data In
Data Hold after Read Data Float after Read
0
ALE Low to Valid Data In
tLLDV
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Port 0 Address, Port 4 CE, Port 5 PCE to Valid Data In Port 2, 4 Address to Valid Data In ALE Low to RD or WR Low Port 0 Address, Port 4 CE, Port 5 PCE to RD or WR Low Port 2, 4 Address to or WR Low Data Valid to WR Transition Data hold after WR high
tAVDV1
tAVDV2
tLLWL
tAVWL1
tAVWL2
tQVWX tWHQX
0.75 tMCS -20 (C ST +0.375)*tMCS -20 (C ST +1.375)*tMCS -20 0.875 tMCS -20 (C ST +0.5)*tMCS -20 (C ST +1.5)*tMCS -20 0.125 tMCS -5 0.125 tMCS +5 0.25tMCS -5 0.25tMCS +5 1.25 tMCS -10 1.25 tMCS +10 0.25 tMCS -5 0.5tMCS -5 2.5 tMCS -10 0.375 tMCS -5 0.625tMCS -5 2.625 tMCS -10 -5 0.25 tMCS -5 0.5tMCS -5 1.5 tMCS -10 0 0.25 tMCS -5 1.25 tMCS -10 -(0.125 tMCS -5) 10 0.25 tMCS +5 1.25 tMCS +10
ns
ns
ns
ns
ns
CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST =0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7
ns ns CST = 0 1 CST 3 4 CST 7 0 CST 7 CST = 0 1 CST 3 4 CST 7
Low to Address Float RD or WR High to ALE, Port 4 CE or Port 5 PCE High
RD
tRLAZ tWHLH
ns ns
NOTES FOR MOVX CHARACTERISTICS:
1. All parameters apply to both commercial and industrial temperature operation unless otherwise noted. 2. CST is the stretch cycle value as determined by the MD2, MD1, & MD0 bits of the CKCON register. tMCS is a time period determined by the stretch cycle value, shown in the following table.
tMCS TIME PERIODS
System Clock Selection CD1 CD0 4X/ 2X 1 0 0 0 0 0 X 1 0 X 1 1 tMCS 1 tCLCL 2 tCLCL 4 tCLCL 1024 tCLCL
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gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg
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lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllloooooooooooooooooooooooooooooooooooooooooo
k
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MULTIPLEXED 2 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE
MULTIPLEXED 2 CYCLE DATA MEMORY CE0 - 3 READ
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MULTIPLEXED 2 CYCLE DATA MEMORY CE0 - 3 WRITE
MULTIPLEXED 3 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE
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MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 READ
MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 WRITE
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MULTIPLEXED 9 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE
MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 READ
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MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 WRITE
ELECTRICAL CHARACTERISTICS (Non-multiplexed address/data bus)
40 MHz PARAMETER SYMBOL MIN MAX Oscillator Freq. (Ext. Osc) 1 / tCLCL 0 40 (Ext. Crystal) 1 40 tPLPH PSEN Pulse Width tPLIV PSEN Low to Valid Instruction In tPXIX 0 Input Instruction Hold after PSEN tPXIZ Input Instruction Float after PSEN Port 1 Address, Port 4 CE to Valid Instruction In Port 2, 4 Address to Valid Instruction In tAVIV1 tAVIV2 VARIABLE CLOCK MIN MAX 0 40 1 40 0.5 tMCS - 5 0.5 tMCS - 20 0 See MOVX characteristics 0.75 tMCS - 20 0.875 tMCS - 25 UNITS MHz ns ns ns ns ns ns
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
1. All parameters apply to both commercial and industrial temperature operation unless otherwise noted. 2. The value tM CS is a function of the machine cycle clock in terms of the processor's input clock frequency. These relationships are described in the "Stretch Value Timing" table. 3. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN , RD and WR with 100 pF. 4. Interfacing to memory devices with float times (turn off times) over 25 ns may cause bus contention. This will not damage the parts, but will cause an increase in operating current. 5. Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change in relation to duty cycle variation.
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NON-MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE
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MOVX CHARACTERISTICS (Non-multiplexed address/data bus)
PARAMETER SYMBOL MIN MAX UNITS STRETCH VALUES CST (MD2:0) CST =0 1 CST 3 ns 4 CST 7 ns ns ns 0.5 tMCS -20 CST *tMCS -20 0 0.5 tMCS -5 0.75tMCS -5 1.75 tMCS -5 0.5 tMCS -5 0.75tMCS -5 2.75 tMCS -5 0.5 tMCS -5 0.75tMCS -5 2.75 tMCS -5 0.75 tMCS -20 (C ST +0. 5)*tMCS -20 (C ST +2.5)*tMCS -20 0.875 tMCS -20 (C ST +0.625)*tMCS -20 (C ST +2.625)*tMCS -20 0.25 tMCS -5 0.5tMCS -5 2.5 tMCS -10 0.375 tMCS -5 0.625tMCS -5 2.625 tMCS -10 -5 0.25 tMCS -5 0.5tMCS -5 1.5 tMCS -10 0 0.25 tMCS -5 1.25 tMCS -5 ns ns ns CST =0 1 CST 7 CST =0 1 CST 7 CST = 0 1 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7 CST = 0 1 CST 3 4 CST 7
Input Instruction Float after
PSEN PSEN High to Data Address,
tPXIZ
tPHAV tRLRH tWLWH tRLDV tRHDX tRHDZ
0.5 tMCS -5 0.75 tMCS -5 2.75 tMCS -10 0.25 tMCS -5 0.5 tMCS -5 CST *tMCS -10 0.5 tMCS -5 CST *tMCS -10
Port 4 CE, Port 5 PCE Valid RD Pulse Width
WR Pulse Width
RD
Low to Valid Data In
Data Hold after Read Data Float after Read
PSEN High to WR Low
tPHWL
ns
Data Float after Read
tPHRL
ns
Port 1 Address, Port 4 CE, Port 5 PCE to Valid Data In Port 2, 4 Address to Valid Data In Port 0 Address, Port 4 CE, Port 5 PCE to RD or WR Low Port 2, 4 Address to RD or WR Low Data Valid to WR Transition Data hold after WR high
tAVDV1
ns
tAVDV2
ns
tAVWL1
ns
tAVWL2
ns
tQVWX tWHQX
ns ns
or WR High to ALE, Port 4 CE or Port 5 PCE High
RD
tWHCEH
10 0.25 tMCS +5 1.25 tMCS +5
ns
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Ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc
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ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc
c
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NON-MULTIPLEXED 2 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE
NON-MULTIPLEXED 2 CYCLE DATA MEMORY CE0 - 3 READ
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NON-MULTIPLEXED 2 CYCLE DATA MEMORY CE0- 3 WRITE
NON-MULTIPLEXED 3 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE
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NON-MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 READ
NON-MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 WRITE
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NON-MULTIPLEXED 9 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE
NON-MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 READ
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NON-MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 WRITE
tMCS TIME PERIODS
System Clock Selection CD1 CD0 4X/ 2X 1 0 0 0 0 0 X 1 0 X 1 1 tMCS 1 tCLCL 2 tCLCL 4 tCLCL 1024 tCLCL
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER Clock high time Clock low time Clock rise time Clock fall time SYMBOL tCHCX tCLCX tCLCH tCHCL MIN 8 8 MAX UNITS ns ns ns ns
4 4
EXTERNAL CLOCK DRIVE
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SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER Serial port clock cycle time SM2=0:2 clocks per cycle SM2=1:4 clocks per cycle Output data setup to clock rising SM2=0:12 clocks per cycle SM2=1:4 clocks per cycle Output data hold from clock rising M2=0:12 clocks per cycle SM2=1:4 clocks per cycle Input data hold after clock rising SM2=0:12 clocks per cycle SM2=1:4 clocks per cycle Clock rising edge to input data valid SM2=0:12 clocks per cycle SM2=1:4 clocks per cycle SYMBOL tXLXL TYPICAL 12 tCLCL 4 tCLCL tQVXH 10 tCLCL 3 tCLCL tXHQX 2 tCLCL tCLCL tXHDX tCLCL tCLCL tXHDV 11 tCLCL 3 tCLCL ns ns ns ns ns ns ns ns UNITS ns ns
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SERIAL PORT 0 (SYNCHRONOUS MODE)
HIGH-SPEED OPERATION, TXD CLK = XTAL/4 (SM2 = 1)
TRADITIONAL 8051 OPERATION, TXD CLOCK=XTAL/12 (SM2=0)
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EXPLANATION OF AC SYMBOLS
This microcontroller uses timing parameters and symbols similar to the original 8051 family. The following list of timing symbols is provided as an aid to understanding the timing diagrams. t A C CE D H L I Time Address Clock Chip Enable Input data Logic level high Logic level low Instruction P Q R V W X Z
PSEN
Output data RD signal Valid WR signal No longer a valid logic level Tristate
POWER CYCLE TIMING CHARACTERISTICS
PARAMETER Crystal start-up time Power-on reset delay SYMBOL tCSU tPOR TYP 1.8 MAX 65536 UNITS ms tCLCL NOTE 1 2
NOTES FOR POWER CYCLE TIMING CHARACTERISTICS
1. Start-up time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz crystal manufactured by Fox Electronics. 2. Reset delay is a synchronous counter of crystal oscillations during crystal start-up. Counting begins when the level on the XTAL1 input meets the VIH2 criteria. At 40 MHz, this time is approximately 1.64 ms.
POWER CYCLE TIMING
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68-PIN PLCC
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64-PIN LQFP
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DATA SHEET REVISION SUMMARY
The following represent the key differences between the 092499 and the 101999 version of the DS80C390 data sheet. Please review this summary carefully. 1. 2. 3. 4. Corrected P5.2 and P5.3 pin descriptions. Corrected description of sequence to activate the crystal frequency multiplier. Corrected references to PQFP to read LQFP. Added RSTOL timing information.
The following represent the key differences between the 062299 and the 090799 version of the DS80C390 data sheet. Please review this summary carefully. 1. Clarifies that unused/unimplemented bits in the CAN MOVX SRAM will read 0. 2. Corrected the tMCS time periods tables. 3. Corrected multiplexed 2-cycle date memory CEO-3 read figure to show RD and WR inactive.
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